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RFC: Phase-Transition Gates for ISC traceability

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Assessment

Difficulty
5/5
Estimated time
Over a week
Newbie friendliness
25/100
Issue type
Feature
Clarity
Needs clarification
Activity status
Stale
Domain
documentation

Research direction

Read the linked full gate specifications and compare them with the existing v1.6.0 entry and exit gates described in the issue. Determine whether the proposal belongs in the main spec or a separate gates module, and whether all four gates or a focused ISC-Map Gate should be adopted; done means the scope and placement are agreed and documented.

Written by the indexing model from the issue text.

Description

Problem

I've been using TheAlgorithm daily and noticed 3 failure modes that occur between phases:

  1. Silent mutations — THINK's pressure test sometimes changes ISC criteria, but there's no explicit checkpoint tracking what changed. PLAN can end up working against stale criteria.

  2. Scope creep in BUILD — The model creates artifacts that weren't in the execution plan and have no ISC backing. The work gets done, but it's untracked and unverifiable.

  3. Rubber-stamp verification — VERIFY runs and produces "PASS" claims, but the verification methods aren't actually executable at that point (e.g., server not running, test file doesn't exist).

v1.6.0 has strong entry gates (Quality Gate after OBSERVE) and exit gates (Verify Completion Gate before LEARN), but the transitions between THINK→PLAN→BUILD→EXECUTE→VERIFY have no checkpoints.

Proposed Solution: 4 Phase-Transition Gates

Simple checklist patterns (no new tools) that sit between existing phases:

Gate Location Catches
Mutation Gate THINK → PLAN Unacknowledged ISC changes from pressure test
ISC-Map Gate PLAN → BUILD Plan steps without ISC backing, ISC without plan steps
Drift-Check During BUILD Artifacts being built without ISC mapping
Verify-Readiness Gate EXECUTE → VERIFY Verification methods that aren't actually executable

Each gate is OPEN or BLOCKED — binary, no ambiguity.

Full Spec

I've written up the complete gate specifications with rationale and examples:

👉 https://gist.github.com/Scaniani/827cc432c0db325ac52673141c7bfd2b

Design Principles

  • Zero new tools — These are patterns, not infrastructure
  • Effort-scaled — Mental checks at Fast/Standard, explicit output at Extended+
  • Backwards-compatible — They extend v1.6.0, don't modify existing gates
  • Tested — I've been running these daily for ~2 weeks across different task types

Questions for Discussion

  1. Would this be useful upstream, or is this too opinionated for the core spec?
  2. If useful — should these be in the main spec or a separate "gates" module?
  3. The ISC-Map Gate is the most impactful in my experience. Would a single-gate PR be preferred over all 4?

Happy to submit a focused PR if there's interest. Just wanted to check alignment first.

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First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

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