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chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilogStars 351Forks 83Watchers 351Open issues 71License ISC License
Details
仓库信息
Ownerchipsalliance
Homepagehttps://chipsalliance.github.io/sv-tests-results/
GitHubhttps://github.com/chipsalliance/sv-tests
Last pushed2025-12-12
Last updated2025-12-15
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