chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

C++Stars 430Forks 77Watchers 430Open issues 47License Apache License 2.0

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仓库信息

Ownerchipsalliance

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GitHubhttps://github.com/chipsalliance/Surelog

Last pushed2025-09-06

Last updated2025-12-15

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chipsalliance/Surelog

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