The-OpenROAD-Project/OpenROAD

Add some good examples from antonblanchard/vlsiffra as a regression test / benchmark

Open

#2,361 opened on Oct 12, 2022

View on GitHub
 (8 comments) (0 reactions) (2 assignees)Verilog (2,715 stars) (903 forks)auto 404
Stalegood first issue

Description

@antonblanchard just released the vlsiffra project. See the tweet @ https://twitter.com/antonblanchard/status/1580154261962657792 

Introducing https://github.com/antonblanchard/vlsiffra/ - a generator of fast and efficient standard cell adders, multipliers and multiply-adders. Written in Amaranth HDL, formally verified with #Yosys. #Verilator verification too With @OpenROAD_EDA + ASAP7 7nm a 32bit 3 cycle multiplier hits 2.7GHz

Some interesting aspects;

  • vlsiffra is written in the Amaranth HDL language which allows it to be very configurable, including
  • vlsiffra currently supports the SkyWater sky130hd, GlobalFoundries GF180MCU and ASAP7 PDKs and standard cell libraries.
  • vlsiffra only requires a few standard cells (full and half adders, 2 input xor, 2 input and, inverter as well as a couple of more complicated cells (ao21, ao22, ao33)

It seems like some of the output of this tool would make excellent OpenROAD regression tests / benchmarks.

Contributor guide