Krishnarjunmitra/Verilog-Projects

Verilog-Projects is a curated collection of RTL design and verification modules, ranging from basic logic circuits (Half Adder, Full Adder) to advanced system-level blocks (ALU, UART, RISC CPU).

VerilogStars 1Forks 0Watchers 1Open issues 1License MIT License
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OwnerKrishnarjunmitra
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Last pushed2025-08-27
Last updated2025-12-14
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